1. Field of the Invention
The present invention relates to a device and method for protecting a semiconductor device, and more particularly, to an n-type metal-oxide semiconductor (NMOS) transistor having a ladder structure, used as a device for protecting a semiconductor device.
2. Description of the Related Art
Semiconductor devices often include an input/output protection circuit to protect internal circuits of the semiconductor device against high voltages, such as the voltages caused by electrostatic discharge (ESD), which can be inadvertently applied to an input terminal or an output terminal of the internal circuits. Conventional protection devices employ a diode, a resistor or a transistor to protect the internal circuits of the semiconductor device. Among these devices, the transistor, typically, an n-type metal-oxide semiconductor (NMOS) transistor, has the disadvantage that the leakage current is large compared to the diode. However, the NMOS transistor is typically used for a complementary MOS (CMOS) circuit because the protection characteristics, such as trigger voltage, snap-back voltage and dynamic resistance, are excellent as compared to the other devices.
A typical NMOS transistor structure consists of a p-type substrate or well, n.sup.+ -type source and drain regions, and a gate formed on the p-type substrate. When an NMOS transistor is used as a protection device, the transistor's gate, the well and the source are grounded and the drain is connected to the pad of either an input or output terminal.
The protection level of the NMOS transistor is greatly influenced by the width of the gate. Generally, the wider the gate, the better the protection level. However, the width of the gate often cannot be increased in one dimension because of size or layout limitations of the semiconductor chip. When the gate size is limited in one dimension, a ladder or finger structure is typically used to increase the gate area.
FIG. 1 is a layout of a conventional MOS transistor with a ladder structure.
First, a gate pattern 1 is formed consisting of a main line and several gate branches G which branch out perpendicularly from the main line of the gate pattern 1.
Next, a drain pattern 3 is formed consisting of a main line and several drain branches D which branch out perpendicularly from the main line of drain pattern 3.
Finally, a source/well pattern 2 is formed consisting of a source/well main line and a pair of source branches S and a pair of source/well branches S/W branching perpendicularly from the source/well main line where the pair of source branches S lie within an area between the pair of source/well branches S/W.
The main lines of patterns 1, 2 and 3 are parallel to each other with the drain main line lying to one side of the gate main line and the source/well main line lying to the other side of the main line.
The source, source/well, gate and drain regions of patterns 1, 2 and 3 are also parallel to one another with each drain branch D being on one side of a gate branch G and either a source branch S or a source/well region being on the other side.
In addition, the gate branches G and drain branches D extend outward from their respective main lines in the same direction while the source branches S and pair of source/well branches S/W extend outward from the main line of pattern 2 in the opposite direction.
The source branch S and drain branch D are connected to an n-type region 40 of a semiconductor substrate through several source contact holes 10 and drain contact holes 30, respectively. The source/well branches S/W, positioned at each end of the transistor, are connected to a p-type region 50, which is typically a well region of the semiconductor substrate through well contact holes 20, and to the n-type region 40 through source contact holes 10. In addition, the main line of the source/well pattern 2 is connected to the p-type region 50 through well contact holes 20. As a result, the MOS transistor formed by the ladder structure is surrounded by source contact holes 10 and well contact holes 20.
Finally, the drain pattern 3 is connected either to an input or output terminal and the source pattern 2 is grounded.
However, the conventional ladder structure described above has the disadvantage that the electrostatic protection level is reduced because of the low voltage breakdown of the device caused by current localization.
Current localization occurs because there is a difference between the resistance values due to the difference in distance between the well contact holes 20 and the source contact holes 10. The farther a source region is from a well contact hole 20, the greater will be the value of the resistance between the source region and the well area 50. The source region which is farthest from a well contact hole 20 is turned ON first when a positive static electric charge is applied to the drain when the source and well are grounded. The discharge rate of the device deteriorates since the current is localized toward the drain region D which is nearest to the turned ON source region, when the source is forward biased.